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Seminar and Session Descriptions
| Tuesday, December 9th |
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8:30am-Noon
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Tutorial T1A: FPGA-Based System Design Organizer: Kevin Morris, FPGA Journal
Instructors:
Security Solutions with Partial Reconfiguration
Eric Shiflet, Xilinx
Holistic FPGA Configuration
C.J. Clark, Intellitech
Double Impact — Leveraging Physical Synthesis for Timing Closure
Rakesh Jain, Mentor Graphics
Shortening FPGA Design Cycles
Lawrence Romine and Ben Jordan, Altium
Essential Assertions for Your Next FPGA Design
Jerry Kaczynski, Aldec
Graphical System Design for FPGA Programming
Rick Kuhlman, National Instruments
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8:30am-Noon
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Hands-on Session 1: Embedded Design Featuring LabVIEW Real-Time, LabView FPGA, and CompactRIO Instructor: Zach Olson, National Instruments (NI)
Course Description:
Learn firsthand how to design, prototype, and deploy embedded systems using off-the-shelf tools and rapid prototyping hardware in a hands-on environment. Explore leading-edge control design tools and techniques to develop embedded systems. Use National Instruments’ reconfigurable I/O (RIO) hardware to create unique timing and triggering routines, interface to digital protocols, perform digital signal processing (DSP), and implement high-performance computing, true parallelism, high reliability, and tight determinism.
At this session, you will learn how to:
- Design embedded systems with FPGAs,
- Use high-level graphical programming to implement FPGA hardware,
- Architect applications for better code reuse and easier debugging,
- Use toolkits and other LabVIEW features to implement digital filters, Fast Fourier Transforms, digital signal processing, and high-speed I/O.
Intended Audience:
FPGA designers, scientists, technicians, design verification engineers, engineering managers, hardware designers, embedded software engineers, DSP engineers, ASIC designers, instrumentation and control specialists, communications and networking specialists, test engineers, and system analysts and engineers
About the Instructor:
Zach Olson is a regional program manager for embedded and control accounts at National Instruments (NI). He focuses on the use of NI Real-Time and LabVIEW FPGA for advanced feedback control, system simulation, and control system design and implementation. He works with OEM customers to specify and implement controllers using graphical system design. His recent projects include the implementation of an FPGA-based serial communications tester for a major aircraft manufacturer and the development of FPGA-based devices to replace custom VME equipment. With NI since 2001, he holds Bachelor’s and Master’s degrees in mechanical engineering from the University of Utah.
About National Instruments:
National Instruments transforms the way engineers and scientists around the world design, prototype, and deploy systems for test, control, and embedded design applications. By using NI open graphical programming software and modular hardware, customers at more than 25,000 companies annually simplify development, increase productivity, and dramatically reduce time to market. From testing next-generation gaming systems to creating breakthrough medical devices, NI customers continuously develop innovative technologies that impact millions of people. For more than 20 years, NI LabVIEW graphical programming has revolutionized the development of test, measurement, and control applications. The LabVIEW FPGA module extends LabVIEW to the development of FPGA-based applications. NI also provides reconfigurable I/O (RIO) hardware that includes processors, FPGAs, and I/O in several forms suitable for both prototyping and production. For more information, see www.ni.com.
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8:30am-Noon
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Hands-on Session 2: Synchronous DRAM Interfaces in Xilinx FPGAs Instructor: Oliver Garreau and Adrian Cosoroaba, Xilinx
Course Description:
Today’s FPGA systems generally require interfaces to high bandwidth memory systems. This is particularly true for applications in DSP, industrial and process control, test equipment, and instrumentation. Synchronous DRAM is the usual approach to implementing such systems because it offers the highest density at the lowest overall cost. This tutorial will review the basic concepts involved and demonstrate the use of Xilinx’s free memory interface solutions for quickly integrating synchronous DRAMs with digital system designs in both cost-sensitive and high-performance applications. The laboratory session will involve using the Xilinx Memory Interface generator to develop a DDR2 SDRAM memory controller and integrate it with a small test application.
Intended Audience:
FPGA designers, engineering managers, hardware designers, DSP engineers, ASIC designers, instrumentation and communications specialists, and test engineers
About the Organizers:
Oliver Garreau is a Senior Engineering Manager at Xilinx, focused on high-volume FPGA launch and application support. He has 16 years experience in embedded systems engineering and has been heavily involved in developing memory subsystems for processors, microcontrollers, DSP chips, and FPGAs. Before joining Xilinx, he was with STMicro, Siemens, and Infineon. He holds BSEE and MSCS degrees.
Adrian Cosoroaba is Memory Solutions Manager at Xilinx. With Xilinx since 2004, he is currently responsible for worldwide marketing activities related to memory interface solutions. He has 20 years of semiconductor experience in memory, microprocessor applications, and marketing. Before joining Xilinx, Adrian held a range of positions including strategic marketing and applications manager and actively participated in JEDEC industry-standard committees. He holds an MSEE from Ohio State University and a BS in engineering physics from the University of California at Berkeley.
About Xilinx:
Xilinx is the leading innovator of complete programmable logic solutions. Founded in 1984 and headquartered in San Jose, California, Xilinx invented the FPGA and fulfills more than half the demand for the devices today. Xilinx programmable logic provides a revolutionary alternative to custom logic chips that require long design and manufacturing cycles. For more information, see our Website at www.xilinx.com.
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1:00-5:00pm
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Tutorial T1B: Image Processing with FPGAs Organizers: Brian Durwood, Impulse Accelerated Technologies
Instructors:
Low-Cost FPGA Solutions for Video Applications
Asher Hazanchuk, Lattice Semiconductor
FPGA-Based Video Processing
Satish Premanathan, Wipro Technologies
Multicore Processing with FPGAs
Brian Durwood, Impulse Accelerated Technologies
High Definition DVI/HDMI Video System Using Spartan-3A TMDS I/O
Bob Feng, Xilinx
Video System Design with Simulink and Xilinx FPGAs
Alan Hwang, MathWorks; Tim Vanevenhoven, Xilinx
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1:00-5:00pm
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Hands-on Session 3 (repeat of Session 1): Embedded Design Featuring LabVIEW Real-Time, LabView FPGA, and CompactRIO Instructor: Zach Olson, National Instruments
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1:00-5:00pm
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Hands-on Session 4: Introduction to Xilinx Embedded Development Kit (EDK) and the MicroBlaze Instructor: Troy Jones, Avnet
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OPEN - Welcoming Reception and Year-in-Review Panel Chairperson: Dave Bursky, Chip Design Magazine
Panelists:
Rick Kuhlman, National Instruments
Dan Isaacs, Xilinx
Daniel Platzker, Mentor Graphics
Ashok Mehta, DefineView Consulting
Steve Suddarth, FPGA Mission Assurance Center
Malachy Devlin, OpenFPGA/Forasach
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| Wednesday, December 10th |
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Tutorial T2A: Getting Your FPGA Application Up and Running Organizer: Steve Knapp, Prevailing Technology
Chairperson: Lee Goldberg, En-Genius; Lee Goldberg, En-Genius Network
Short Presentations:
Design Tools/Design Portability
Daniel Platzker, Mentor Graphics
Test Tools and Equipment
Steve Knapp, Prevailing Technology
Verification
Dave Orecchio, GateRocket
From System Specification to FPGA Implementation
Sanjay Thatte, Mentor Graphics
Breakout Sessions on:
Design Methods
Daniel Platzker, Mentor Graphics
System Interfacing
Andy Stevens, VMETRO; TBD, Xilinx
Verification
Dave Orecchio, GateRocket
Joint Session and Reports
Design Tips Panel
Chairperson: Lee Goldberg, EnGenius
Panelists:
Daniel Platzker, Mentor Graphics
Alex Vals, Mentor Graphics
Dan Isaacs, Xilinx
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Tutorial T3A: Reconfigurable and High-Performance Computing Organizer: Mike Alford, Gennum
Instructors:
Implementing In-System Reconfiguration
Mike Alford, Gennum
Dimenisions in Reconfigurable Computing
Joseph Hassoun, Element CXI
FPGA Software Acceleration
Stefan Mohl, Mitronics
Intent-Directed Creation of Custom Programmable Debug Fabrics
David Whelihan and Kumar Dwarakanath, DAFCA
Threats and Challenges in FPGA Security
Ted Huffmire, Naval Postgraduate School
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8:30-9:45am
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OPEN - Session 101: Communications/Networking Applications Chairperson: Andy Norton, Cloudshield Technologies
Paper Presenters:
Verifying FPGA Designs with Multiple Asychronous Clocks
Kurt Takara, Mentor Graphics
Breaking the Gigahertz Barrier with Software Offload Engines (SOEs)
Glenn Steiner, Xilinx
FPGA-Based RapidIO Protocol Capture Enables High-Level System Debugging
Alex Gargarita, Lattice Semiconductor and Kent Dahlgren, Praesum Communications
FPGA Accelerated Constrained Random Verification (presentation by Bruce Greene, Synopsys)
Amit Sharma, Synopsys India and Yogesh Mittal, Freescale Semiconductor
Building PCI Express Interfaces in FPGAs
Stephane Hauradou, PLDA
GHz FPGAs for Demanding Applications
Denny Scharf, Achronix
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10:05-11:10am
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OPEN - Session 102: DSP Applications Chairperson: Jag Bolaria, Linley Group
Paper Presenters:
Direct Progarmming of Multi-FPGA Platform from a Single Simulink Model
Stephen Malchi, Sundance DSP
Customization is Key for IPs Used in FPGA Design
Kumar Venkatramani, SoftJin Technologies
Choosing the Best DSP Architecture Implementation for Your FPGA Design
Roger Do, Mentor Graphics
Analyzing Programmable SOC Processing for High Performance Streaming Applications
David Pellerin, Impulsa Accelerated Technologies and Dan Isaacs, Xilinx
Rapid Development of Hybrid (FPGA and DSP) Signal Processing Applications
Jeff Milrod, BittWare
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11:20am-Noon
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OPEN - Keynote 1: Concept-to-Gates Design — 2008 and Beyond
Speaker: Simon Bloch, Mentor Graphics
Introducer: Kevin Morris, FPGA Journal
Abstract:
System-level design, combining ESL (electronic system-level design) and RTL(register transfer level), will drive a new era in FPGA design methodology.
System-level approaches are gaining importance as devices become larger and more complex. Higher-level abstraction is essential in designing multi-million gate SoCs as well as FPGAs. It extends the traditional RTL design flow by integrating higher-level languages in C++ and transaction-level modeling in SystemC, enabling efficient evaluation of various architectural scenarios for a hardware/software system. By taking this approach, designers can address power, performance, and area challenges at the earliest conceptual stages. Handling such issues early in the design cycle is often the key to making a critical market window.
About the Speaker:
Simon Bloch is Vice-President and General Manager of Mentor Graphics’ ESL/RTL design and synthesis division. He joined Mentor in 2002 as general manager of the FPGA synthesis business. He later assumed responsibility for HDL design tools, high-level synthesis, and ESL design. Before joining Mentor Graphics, Bloch served as CEO and founder of Aristo Technology and held senior management positions at VLSI Technology, Compass Design Automation, and Daisy Systems. He began his career at Tadiran Communications in 1982 designing ASICs and systems for telecommunications applications. He holds a Bachelor’s degree in electrical engineering from Tel Aviv University.
About Mentor Graphics:
Mentor Graphics® is a technology leader in electronic design automation (EDA), providing software and hardware design solutions that enable companies to develop better electronic products faster and more cost-effectively. The company offers innovative products and solutions that help engineers overcome the design challenges they face in the increasingly complex worlds of board and chip design. Mentor Graphics has the broadest industry portfolio of best-in-class products and is the only EDA company with an embedded software solution. For more information, see www.mentor.com. |
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2:00-2:30pm
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OPEN - Keynote 2: Tipping Points in Programmable Logic: Is FPGA Design More Complex than ASIC Design? Speaker: Andrew Dauman, Vice President, Engineering, Synopsys
Introducer: Jim Harrison, Electronic Products
Abstract:
In programmable logic’s 25-year history, we have seen continuous major improvements in both the devices themselves and their associated software. Often the changes follow certain themes that reflect the end markets being served. How are the markets shifting and why? What are the themes dominating software development projects at both device vendors and EDA vendors?
In this keynote speech, Andrew Dauman will outline Synopsys’ vision of the challenges and opportunities ahead in programmable logic. What are design teams around the world seeking to improve their productivity and realize the promise of programmable logic? How can Synopsys better serve those needs now that it offers both its traditional ASIC tools and the FPGA tools pioneered by Synplicity?
About the Speaker:
Andrew Dauman, in his role as vice president of engineering for Synopsys’ Synplicity Business Group, oversees the development of programmable solutions for FPGA Implementation, ASIC verification, and ESL/DSP algorithm implementation.
Before joining Synopsys, Mr. Dauman was Vice President of Engineering and Vice President Corporate Applications Engineering for Synplicity, which Synopsys acquired in May 2008. Mr. Dauman previously held positions at Mentor Graphics, Silicon Compiler Systems, Prime Computer, and Raytheon. He has a BSEE from Boston University.
The Synplicity Business Group of Synopsys provides innovative IC design and verification solutions that serve a wide range of communications, military/aerospace, semiconductor, consumer, computer, and other applications markets. The FPGA implementation tools provide outstanding performance, cost, and time-to-market benefits by simplifying, improving, and automating logic synthesis, physical synthesis, analysis, and debug for programmable logic designs. Synplify DSP, the company’s high-level algorithmic synthesis product, significantly improves productivity for DSP designs realized in ASICs and FPGAs. The Confirma™ rapid prototyping platform, comprising software tools and the HAPS™ family of prototyping systems, enables both comprehensive verification of ASIC, ASSP, and SoC designs and software development prior to chip tapeout. Synopsys is the leading supplier of FPGA synthesis tools, and Synplicity Business Group’s physical synthesis and ASIC verification technologies are the recipients of several prestigious industry awards.
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Tutorial T2B: Getting Your FPGA Application Done on Time, On-Budget, and Within Specs Organizer: Ehab Mohsen, Mentor Graphics
Instructors:
FPGA Project Time and Cost Estimation
TBD
Avoid FPGA Project Delays by Adopting Advanced Design Methodologies
Alex Vals, Mentor Graphics
Building an FPGA Design Repository
Tom Dewey, Mentor Graphics
Power Optimization for FPGA Designs
Matt Klein, Xilinx
Converting Designs Written in C into FPGAs
Fernando Martinez, Synfora
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Tutorial T3B: FPGA Verification Organizer: Dave Orecchio, GateRocket
Instructors:
Recalculating the Road to Successful FPGA Verification
Joe Rodriguez, Mentor Graphics
A Case for Hardware-Assisted Verification
Chris Schalick, GateRocket
FPGAs Increasing Role in Development
James Smith, Altera
FPGA-Based DDR Memory Controller Validation
Judith Smith, Agilent Technologies
Platform FPGA Automated Regression Test Methodology
Peter Ryser and Dan Isaacs, Xilinx
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OPEN - Session 103: Military/Defense/Aerospace Applications Chairperson: Chris Ciufo, Military Embedded Systems
Paper Presenters:
Solutions for DO-254 Compliant FPGA Design
Michelle Lange, Mentor Graphics
The FMC (VITA 57) Standard Makes FPGAs Easier to User
Dave Barker, VMetro
Build vs. Buy: The Battleground of COTS Hardware
Rick Kuhlman, National Instruments
Rapid Implementation of FPGAs in Challenging Communications System Architecture
Daren McClearnon, Agilent EEsof
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OPEN - Session 104: Power Issues Chairperson: Jim Harrison, Electronic Products
Paper Presenters:
Powering Serdes Interfaces
William Troutman, Enpirion
Intelligent Power Management of FPGAs
Steve Herhusky, Arrow Electronics
Power Aware Verification for FPGA Designs
Abhishek Kesh, Mentor Graphics
Design Techniques to Minimize System Power
Hezi Saar, Actel
Adaptive Circuit Implementation in FPGAs
Srikanth Devarapalli, University of New Mexico
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7:00-8:30pm
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OPEN - Beer, Pizza and Chat with the Experts (featuring tables on specific subjects presided over by experts) Organizer: Steve Knapp, Prevailing Technology
Table Leaders:
EDA Tools
Jim Smith, Altera and Lawrence Romine, Altium
Verification
Dave Orecchio, GateRocket
Reconfigurable Computing
Joseph Hassoun, element CXI and Mike Alford, Gennum
Military/Defense/Aerospace Applications
Michelle Lange, Mentor Graphics and Ken LaBel, NASA Goddard
Consumer Applications
Bob Feng, Xilinx
Security
Rich Fetik, Data Confidential and Eric Shiflet, Xilinx
DSP Applications
Jeff Milrod, BittWare and Michael Parker, Altera
Intellectual Property
Nilesh Amin, GDA Technologies and John Swan, Swan-on-Chips
Low-power Design
Hezi Saar, Actel and Steve Herhusky, Arrow
Communications/networking Applications
Jag Bolaria, Linley Group and Andy Norton, Cloudshield Technologies
High-Performance Computing
Glenn Steiner, Xilinx
Speeding up development
Brian Durwood, Impulse Accelerated Technologies and Daren McClearnon, Agilent EEsof
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| Thursday, December 11th |
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8:30-9:45am
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Session 201: The Customer Talk Back Chairperson: Dan Harris, NapkinLinks.com
Panelists:
System on Chip Features Bring a New Level of Integration to FPGA Design
Andy Norton, Cloudshield Technologies
FPGA-Based 802.3 Standard Compliance Test Tools
Dave Estes, UNH-IOL
From the Earth to Mars: FPGAs in Space Applications
Ken LaBel, NASA Goddard
Symbolic Computing with FPGAs
Michael Leventhal and Eric Lemoine, LSI
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8:30-9:45am
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OPEN - Session 202: Applications Chairperson: Jerry Gipper, Embedded Systems Design
Paper Presenters:
Protect Your FPGA IP Against Piracy
Dave Bursky, Maxim Integrated Products
Challenges in SoC System Integration Before Silicon Using FPGAs
Shyam Uma-Chander, Gidel
Transaction-Level Emulation
Alain Raynaud, EVE-USA
Designing Portable Clinical and Home-Based Medical Systems
Hezi Saar, Actel
Choosing the Right Flash Memory for FPGA-Based Designs
Olivier Mardinian, Spansion
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10:00-11:10am
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OPEN - Session 203: Market Research Chairperson: Rich Fetik, Data Confidential
Panelists:
Joe Byrne, Linley Group
Gary Smith, Gary Smith EDA
Eric Heikkila, Venture Development
FPGA Design Future - and EE Times Survey
Craig Kief, FPGA Mission Assurance Center
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10:00-11:10am
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Chairperson: Mike Santarini, Xilinx
Paper Presenters:
Multiple-FPGA Partition
Nang-Ping Chen, Auspy Development
High-Performance Interface Intellectual Property for FPGAs
Nilesh Amin, GDA Technologies
Automating FPGA-Based System Design
Nagesh Gupta, Taray
Incremental Synthesis for Design Iterations
Shantanu Kamat, Mentor Graphics
An Effective FPGA/PCB Co-Design Process
Bob Potock, Mentor Graphics
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11:20am-Noon
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OPEN - Keynote 3: Multiprocessing for Higher Performance and Lower Power
Speaker: Danny Biran, Senior Vice President, Product and Corporate Marketing, Altera
Introducer: Jerry Gipper, Embedded Systems Design
Abstract:
In the new era of high energy costs and stringent environmental regulations, next-generation electronic applications will require more efficient power management, while still meeting ever-increasing performance goals. To meet these dual demands, the industry must look to flexible technology that saves power and boosts performance simultaneously. Because of their unique capabilities, FPGAs are an ideal approach. Advances in FPGAs and their associated tools now allow designers to use hardware acceleration to combine unparalleled performance with the lowest possible power footprint.
About the Speaker:
Danny Biran joined Altera in January 2005 as vice president, product and corporate marketing with over 20 years of semiconductor industry experience. Most recently, he served as the president, CEO, and member of the board of directors of Silverback Systems, a privately-held company that develops silicon solutions for storage networks. Prior to that, Biran held vice president and general management positions at LSI Logic and several engineering management and marketing positions at National Semiconductor. He holds BSEE and MBA degrees from Tel Aviv University.
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2:00-3:30pm
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OPEN - Session 205: Top Ten Things You Need to Know about FPGAs Today Chairperson: Kevin Morris, FPGA Journal
Panelists provide their ideas on what one needs to know, the audience offers contributions, and everyone votes on a final top ten to be posted on the Web.
Panelists:
David Pellerin, Impulse Accelerated Technologies
Andy Norton, Cloudshield Technologies
Navneet Rao, Xilinx
Daniel Platzker, Mentor Graphics
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